1. Field of the Invention
The present invention is generally directed to high speed memory systems. More particularly, the present invention is directed to improved signaling of data status within a computing system.
2. Background Art
A data bus is susceptible to cross talk, simultaneous switching noise, inter symbol interference, and draws power based on the state of the data and/or frequency of data transition. One way to reduce these adverse effects and to prevent unnecessary power consumption is to encode the data. One specific form of data encoding that can be used is data bus inversion (DBI).
Implementation of DBI includes encoding circuitry at the transmitter that assesses the relationship between data bits to be transmitted across a data bus and then decides (based on a particular DBI algorithm) if it would be advantageous to invert some or all of the data bits prior to transmission. If the data bits are inverted, an additional signal, referred to as a DBI bit, is also set at the encoding circuitry to indicate that the data bits are inverted. Typically, an extra channel is needed so that the DBI bit may be transmitted in parallel with the data bits to inform the receiving circuitry which groups of data bits have been inverted. A receiver then uses the DBI bit in conjunction with decoding circuitry to return the incoming group of data bits to their original state.
Another form of status signaling is used in conjunction with dynamic random access memory (DRAM). DRAMs may be used for the main memory of a computer system, and also may be used in graphics applications. DRAMs may include a data masking function to mask data that is input via data input and output pins (typically called “DQ pins”) from an external source. Data masking generally is performed in units of a single byte and is signaled through the use of a data masking hit or line. For example, in the case of a synchronous DRAM having a data path width of 16 bits, there are generally two data masking pins (typically called “DQM pins”) from which data masking signals are input. These DQM pins comprise a lower DQM (LDQM) pin and an upper DQM (UDQM) pin. The UDQM pin masks data input via data input and output pins DQ0 through DQ7, e.g., the lower 8 bits of 16 bits that are input via 16 data input and output pins DQ1 through DQ15. The UDQM pin masks the upper 8 bits, data input via data input and output pins DQ8 through DQ15 where pins include any input/output structure for an integrated circuit (IC) device and can include pads, optical input/output structures and other conventional input/output structures.
Therefore, an IC memory device can include multiple pins, or lines, that indicate the status of data on a data bus, e.g., DBI and/or masking. Such a device may also use a single control line to indicate the status of a data bus, but utilize multiple clock cycles to convey multiple status states that are associated with the data.